چیت‌شیت Verilog

1always_ff @(posedge clk) begin2    if (reset) begin3        q <= '0;4    end else begin5        q <= data_in;6    end7end

1always_ff @(posedge clk or negedge reset_n) begin2    if (!reset_n)3        q <= '0;4    else5        q <= data_in;6end

1always_ff @(posedge clk or negedge reset_n) begin2    if (!reset_n)3        count <= '0;4    else if (enable)5        count <= count + 1'b1;6end

1typedef enum logic [1:0] {IDLE, BUSY, DONE} state_t;2state_t state, next_state;34always_comb begin5    next_state = state;6    case (state)7        IDLE: if (start) next_state = BUSY;8        BUSY: if (finished) next_state = DONE;9        DONE: next_state = IDLE;10        default: next_state = IDLE;11    endcase12end

1initial clk = 1'b0;2always #5 clk = ~clk;34initial begin5    reset_n = 1'b0;6    repeat (2) @(posedge clk);7    reset_n = 1'b1;8end

1assert property (@(posedge clk)2    disable iff (!reset_n)3    valid |-> !$isunknown(data)4);